The present invention relates to a solid-state imaging apparatus having a frame transfer or frame interline type solid-state imaging device.
FIG. 1 is a block diagram showing an imaging apparatus that has a frame transfer type CCD 1 (solid-state imaging device). FIG. 2 is a timing chart illustrating the operation of the imaging apparatus.
The CCD 1 includes a light receiving portion 1a, a storing portion 1b, a horizontal transfer portion 1c, and an output portion 1d. The light receiving portion 1a has a plurality of shift registers arranged parallel to one another in the vertical direction. Each bit of the shift registers forms a light receiving pixel. Each light receiving pixel stores an information charge generated in correspondence with a sensed object. The storing portion 1b has a plurality of shift registers arranged continuously from the shift registers of the light receiving portion 1a. Further, the storing portion 1b temporarily stores information charges that correspond to a single image output by the light receiving portion 1a. The number of bits in each shift register is determined in accordance with the number of bits in the shift registers of the light receiving portion 1a. The horizontal transfer portion 1c has a single shift register, each bit of which is connected to the output of an associated storing portion 1b shift register. Further, the horizontal transfer portion 1c receives the information charges, which correspond to a single image, line by line and sequentially transfers each line of information charges. The output portion 1d has an electrically independent capacitor and an amplifier for extracting fluctuations in the potential of the capacitor. The capacitor receives the information charge from the horizontal transfer portion 1c in units of single pixels. The output portion 1d converts the information charge into a voltage value and generates an image signal Y.
A vertical drive circuit 2, which is operated in accordance with a vertical timing signal VD, generates a vertical transfer clock φv from a reference clock MCK, which has a predetermined cycle, and sends the vertical transfer clock φv to the light receiving portion 1a and the storing portion 1b. When the light receiving portion 1a receives the vertical transfer clock φv, the information charges stored in the light receiving pixels are immediately transferred to the storing portion 1b in units of single images. A horizontal drive circuit 3, which is operated in accordance with a horizontal timing signal HD, generates a storage transfer clock φs from the reference clock MCK. The horizontal drive circuit 3 simultaneously generates a horizontal transfer clock φh. The storage transfer clock φs is provided to the storing portion 1b together with the vertical transfer clock φv. When the storing portion 1b receives the storage transfer clock φs, the information charges stored in the storing portion 1b are transferred to the horizontal transfer portion 1c line by line. The horizontal transfer clock φh is provided to the horizontal transfer portion 1c. When the horizontal transfer portion 1c receives the horizontal transfer clock φh, the information charges transferred to the horizontal transfer portion 1c from the storing portion 1b are sequentially, serially transferred to the output portion 1d. 
A timing control circuit 4 includes a horizontal counter and a vertical counter. The horizontal counter divides the reference clock MCK to generate the horizontal timing signal HD. The vertical counter divides this horizontal timing signal HD to generate the vertical timing signal VD. For example, in accordance with the NTSC standards, the timing control circuit 4 divides the reference clock MCK, the frequency of which is 14.32 MHz, by 910 to generate the horizontal timing signal HD and this horizontal timing signal HD by 252.5 to generate the vertical timing signal VD. The horizontal and vertical timing signals HD, VD respectively represent various timing signals related with horizontal scan periods and vertical scan periods.
The CCD 1 repeats imaging operations in cycles corresponding to the vertical timing signal VD and outputs the image signal Y in units of single lines in cycles corresponding to the horizontal timing signal HD during each vertical scan period.
The exposure time of the CCD 1, or the time period during which an information charge is stored in each light receiving pixel, coincides with the vertical scan cycle when an electronic shutter is not operated. Further, the exposure time may normally be varied by discharging the information charges during the vertical scan period, that is, by operating an electronic shutter. If the imaging apparatus does not have television system restrictions, the frequency of the reference clock MCK may be changed to vary the exposure time.
If the sensed object has a low luminance or if the CCD 1 has a low light receiving sensitivity, the frequency of the reference clock MCK is decreased to lengthen the vertical scan cycle in order to obtain sufficient exposure time. However, when the frequency of the reference clock MCK is decreased, the frequency of the vertical transfer clock φv, which is generated from the reference clock MCK, also decreases. This increases the time required for frame transfer from the light receiving portion 1a to the storing portion 1b and increases smear.